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1I CD20 51
fax id: 3512
ICD2051
Dual Programmable Clock Generator
Features
* Two independent clock outputs ranging from 320 kHz to 100 MHz * Individually programmable PLLs use 22-bit serial word * Low-skew /1,/2, and /4 CLKA outputs * Phase-locked loop oscillator input derived from external low-frequency reference clock (1 MHz - 25 MHz) or external crystal (2 MHz - 24 MHz) * Sophisticated internal loop-filter requires no external components or manufacturing tweaks as commonly required with external filters * Three-state control disables outputs for test purposes (optional) * 5V operation * Low-power, high-speed CMOS technology * Available in 16-pin SOIC package
Functional Description
The ICD2051 Programmable Clock Generator offers two fully user-programmable phase-locked loops in a single package. The outputs may be changed "on the fly" to any desired frequency value between 320 kHz and 100 MHz. The ICD2051 is ideally suited for any design where one or more multiple or varying frequencies are required, thus replacing more expensive metal can oscillators. The capability to dynamically change the output frequency adds a whole new degree of freedom for the electrical engineer. Some examples of the uses for this device include: laptop computers, in which slowing the speed of operation can mean less power consumption or speeding it up can mean faster operation; graphics board dot clocks to allow dynamic synchronization with different brands of monitors or display formats; and on-board test strategies where the ability to skew a system's desired frequency (for example 10%) allows worst case evaluations.
Logic Block Diagram
f(REF) XTALIN /q 7 7 3 Phase Detector Charge Pump VCO
XTALOUT
Internal Loop Filter /2p post-VCO divider select
Code Decode
VCO range select 4 Phase-Locked Loop Oscillator Section A
MUX MUXREFA /2 /4
CLKA
CLKA/2 CLKA/4 XBUF
PLL SectionB SCLKA DATA GND VDD SCLKB MUXREFB 22 Serial Rcvr A
MUX
CLKB
22 Serial Rcvr B
OEA OEB
ICD2051-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 January 1995 - Revised April 1995
ICD2051:1/95
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ICD2051
Pin Configuration
SOIC Top View
SCLKB MUXREFB OEB GND f(REF)/XTALIN XTALOUT XBUF CLKB 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ICD2051-2 DATA MUXREFA OEA VDD SCLKA CLKA/4 CLKA/2 CLKA
Pin Summary
Name SCLKB MUXREFB Number 1 2 Description Serial clock input line for CLKB MUXREFB = 0, CLKB equals input reference frequency MUXREFB = 1, CLKB equals programmed frequency This is used if glitch-free frequency changes are required. Three-states CLKB outputs when pulled LOW. (Internal pull-up allows for no-connect if three-state operation is not needed.) Ground Reference Oscillator input for all internal phase-locked loops Oscillator output to a reference crystal. Buffered Crystal Oscillator Output CLKB Programmable Output CLKA Programmable Output CLKA divided by 2 (low skew) CLKA divided by 4 Serial clock input line for CLKA. +5V Three-states CLKA outputs when pulled LOW. (Internal pull-up allows for no-connect if three-state operation is not needed.) MUXREFA = 0, CLKA equals input reference frequency MUXREFA = 1, CLKA equals programmed frequency This is used if glitch-free frequency changes are required. Serial data input line for both programmable PLLs
OEB GND fREF/ XTALIN[1] XTALOUT[1] XBUF CLKB CLKA CLKA/2 CLKA/4 SCLKA VDD OEA MUXREFA
3 4 5 6 7 8 9 10 11 12 13 14 15
DATA
16
Note: 1. For best accuracy, use a parallel-resonant crystal, assume CLOAD = 17 pF.
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ICD2051
General Considerations
Table 3. Index Field (I) Programming the ICD2051 The desired output frequency is defined via a serial interface, with a 22-bin number shifted in. The ICD2051 has two programmable PLLs (CLKA and CLKB), requiring a 22-bit programming word (W) to be loaded into each channel independently. This word contains 5 fields: Table 1. Programming Word Bit Fields Field Index (I) P Counter value (P') Reserved (R) Mux (M) Q Counter value (Q') # of bits 4 7 1 3 7 LSB (Least Significant Bits) normally set to logic 1 Notes MSB (Most Significant Bits) I 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 f(VCO) (MHz) 40.0 - 42.5 42.5 - 47l.5 47.5 - 53.5 53.5 - 58.5 58.5 - 62.5 62.5 - 68.5 68.5 - 69.0 69.0 - 82.0 82.0 - 87.0 87.0 - 92.0 92.0 - 92.1 92.1 - 105.0 105.0 - 115.0 115.0 - 120.0 115.0 - 120.0 115.0 - 120.0
The frequency of the programmable oscillator f(VCO) is determined by these fields as follows: P'=P-3 Q'=Q-2 f(VCO)=2 x f(REF) x P/Q where f(REF)=Reference frequency (between 1 MHz - 25 MHz) The value of f(VCO) must remain between 40 MHz and 120 MHz. Therefore, for output frequencies below 40 MHz, f(VCO) must be multiplied up into the required range. To accomplish this, a post-VCO Divisor is selected by setting the values of the Mux field (M) as follows: Table 2. Mux Field (M) M 000 001 010 011 100 101 110 111 Divisor 1 2 4 8 16 32 64 128
If the desired VCO frequency lies on a boundary in the table (if it is exactly the upper limit of one entry and the lower limit of the next) then either index value may be used (since both limits are tested), but we recommend using the higher one. To assist with these calculations, Cypress/IC Designs provides BitCalc (Part #ICD/BCALC), a WindowsTM program which automatically generates the appropriate programming words from the user's reference input and desired output frequencies. The software also assembles the program words for control and power-down registers. Contact your local Cypress representative for more information. Programming Constraints There are five primary programming constraints the user must be aware of: Table 4. Programming Constraints Parameter f(REF) f(REF)/Q f(VCO) Q P Minimum 1 MHz 200 kHz 40 MHz 3 4 Maximum 25 MHz 1 MHz 120 MHz 129 130
The Index field (I) is used to preset the VCO to an appropriate range. The value for this field should be should be chosen from Table 3. (Note that this table is referenced to the VCO frequency f(VCO), rather than to the desired output frequency.)
The constraints have to do with trade-offs between optimum speed and lowest noise, VCO stability and factors affecting the loop equation. The factors are listed for completeness sake; however, by using the BitCalc program all of these constraints become transparent. ICD2051 Programming Example The following is an example of the calculations BitCalc performs:
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ICD2051
Derive the proper programming word for a 39.5 MHz output frequency, using 14.31818 MHz as the reference frequency: Since 39.5 MHz<40 MHz, double it to 79.0 MHz. Set M to 001. Set I to 0111. The result: f(VCO)=79.0=(2 x 14.31818 x P/Q) P/Q=2.7857 Several choices of P and Q are available: Table 5. P and Q Value Candidates P 69 80 91 Q 25 29 33 f(VCO) (MHz) 79.0363 78.9969 78.9669 Error (PPM) 460 40 419 glitch-free. (See Serial Programming Timing in the Switching Waveforms section of this datasheet.) Skew-Controlled /2 on CLKA The CLKA output is available concurrently as /1, /2, and /4 values of the desired output. The /1 and /2 outputs are also closely matched in order to minimize the phase differences between the two outputs. Typical phase coherence is less than 2 ns of skew between the two outputs, with 1 ns or less available as an order option. Output Frequency Accuracy The accuracy of the ICD2051 output frequencies depends on the target output frequency. As stated previously, the output frequencies of the ICD2051 are integrally related to the input reference frequency: f(OUT)=2 x f(REF) x P/Q Only certain output frequencies are possible for a particular reference frequency. However, the ICD2051 normally produces an output frequency within 0.1% of the desired output frequency. Specifics regarding accuracy (ppm) are given for any desired output frequency as part of the BitCalc program output. Three-State Output Operation The OEA or OEB signal, when pulled LOW, will three-state the clock output line (CLKA or CLKB respectively). This supports wired-OR connections between external clock lines, and allows for procedures such as automated testing where the clock must be disabled. The OE signals contain internal pull-ups; they can be left unconnected if three-state operation is not required. Estimating Total Current Drain Actual current drain is a function of frequency and of circuit loading. The operating current of a given output is given by the equation: I=C*V*f, where I=current, C=load capacitance (max. 25 pF), V=output voltage (usually 5V), and f=output frequency (in MHz). To calculate total operating current, sum the following: XBUF CLKA CLKA/2 CLKA/4 CLKB Internal C*V*f(REF) C*V*f(CLKA) C*V*f(CLKA/2) C*V*f(CLKA/4) C*V*f(CLKB) 12 mA
Choose (P, Q)=(80,29) for best accuracy (40 ppm). Therefore: P'=P-3=80-3=77=1001101 (4dH) Q'=Q-2=29-2=27=0011011 (1bH) The programming word, W is generated by concatenating I=0111, P'=1001101, R=1, M=001, Q'=0011011 to obtain W=0111100110110010011011 (1e6c9bH) A LOW-to-HIGH transition on SCLKA/SCLKB (depending on appropriate channel) is used to shift the programming word W into DATA as a serial bit stream, LSB first. (See the set-up and hold timing specifications later in this datasheet.) If more than 22 shifts are performed, only the last 22 data bits received will be retained. Glitch-Free Frequency-Modification Procedure When changing to a new frequency, there is a period of time when the output signal will be in transition and may glitch due to changes in the post divider. For applications where it is critical that the output clock not glitch and always maintain some known value, the MUXREFA and MUXREFB inputs must be used. Under normal operation, MUXREF(X) is HIGH and the output clocks are at the programmed value. When MUXREF(X) is brought LOW, the reference clock is now multiplexed to the associated output clock. The output remains at this fixed frequency while the programmed frequency seeks its new value. When programming the ICD2051, use the MUXREF inputs in the following manner: 1. Set MUXREF(X) to a LOW state. This will set the output to the reference frequency. The transition is guaranteed to be glitch-free. (See the timing specifications.) 2. Shift in the desired output frequency value via a 22-bit word (as defined above) using the appropriate SCLK and DATA lines. 3. After the last bit is shifted in, the VCO will settle to the new state (within .01% of the actual output frequency) within 10 msec. 4. Set MUXREF(X) to a HIGH state. This will set the output to the new programmed frequency. This transition is guaranteed to be
This gives an approximation of the actual operating current. For unconnected output pins, one can assume 5-10 pF loading, depending on package type. Typical values: Table 6. Typical Load Current Values Frequency low high high Load none none high Current (mA) 15 40 100
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ICD2051
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage to Ground Potential .................-0.5V to +7.0V DC Input Voltage ......................................... -0.5V to VDD +0.5V Storage Temperature ....................................... -65C to +150C Max soldering temperature (10 sec) ............................ 260C Junction temperature ................................................... 125C Package power dissipation..................................525 mWatts
Operating Range
Ambient Temperature 0C TAMBIENT 70C VDD & AVDD 5V 5%
Operating Conditions
Parameter VDD TA CL Supply Voltage Ambient Operating Temperature Load Capacitance Description Min. 4.75 0 Max. 5.25 70 25 Unit V C pF
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output Leakage Current Power Supply Current IOH = -4.0mA IOL = 4.0 mA Except XTALIN pins Except XTALIN pins VIN = 5.25V VIN = 0V Three-state outputs VDD = VDD max., 100 MHz, VIN = VDD or 0V 15 2.0 0.8 150 -250 10 100 Test Conditions Min. 2.4 0.4 Max. Unit V V V V A A A mA
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ICD2051
Switching Characteristics Over the Operating Range[2]
Parameter f(REF) t(REF) Name Output Frequency Reference Frequency Reference Clock Period Duty Cycle t2 t3 t4 t5 t6 t6H t6L t7 t8 t9 t10 t11 t12 t13 t14 t15 Output Rise Time Output Fall Time CLKA/2/4 skew MUXREF Set-Up Time SCLK Cycle Time SCLK HIGH Time SCLK LOW Time Output Clock Stable Time Data Set-Up Time Data Hold Time Transition Time Transition Time Transition Time Transition Time Output Disable Time Output Enable Time Reference Oscillator nominal value t(REF) = 1/f(REF) Duty cycle for the output oscillators defined as t1A / t1B Rise time for the outputs into a 25-pF load Fall time for the outputs into a 25-pF load Skew delay between the CLKA output and the CLKA/2 and CLKA/4 outputs Delay required after MUXREF goes LOW prior to starting the SCLK clock line Minimum cycle time for the SCLK clock Minimum HIGH time for the SCLK clock Minimum LOW time for the SCLK clock Time required for CLKA or CLKB output to become valid after last SCLK clock Time required for the data to be valid prior to the rising edge of SCLK Time required for the data to remain valid after the rising edge of SCLK Time for CLKA or CLKB to go HIGH after assertion of MUXREF Delay of CLKA or CLKB prior to valid t(REF) signal at output Time for CLKA or CLKB to go HIGH after release of MUXREF Delay of CLKA or CLKB prior to valid new frequency at output Time for the outputs to go into three-state mode after OE signal assertion Time for the outputs to recover from three-state mode after OE signal goes HIGH 10 5 0 t(REF)/2 0 tfreq2/2 tfreq1 3(t(REF)/2) t(REF) 3(tfreq2/2) 12 12 tfreq1 2*t(REF) t(REF) t(REF) 10 Description Min. 0.320 1 40 40% Max. 100 25 1000 60% 3 3 2 ns ns ns ns ns ns ns msec ns ns ns ns ns ns ns ns Unit MHz MHz ns
Note: 2. Input capacitance is typically 10 pF, except for the crystal pads.
Switching Waveforms
Duty Cycle Timing
t1B t1A 1.5V 1.5V 1.5V
ICD2051-3
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ICD2051:1/95
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ICD2051
Switching Waveforms (continued)
Rise and Fall Times
f(REF) ALL INPUT AND OUTPUT CLOCKS t2
90% 10% 90% 10%
t3
t4 CLKA/2 CLKA/4
ICD2051-4
Serial Programming Timing
MUXREFA MUXREFB t5 22 CLOCKS REQUIRED FOR DATA t6 SCLKA SCLKB t7 t6H t6L
t8 DATA t10 CLKA CLKB
t9 DATA VALID t11 t12
t13
tfreq1
ORIGINAL FREQUENCY
t(REF)
REFERENCE FREQUENCY
tfreq2
NEW FREQUENCY
ICD2051-5
Three-State Timing
OEA OEB t14 CLKA CLKB t15 THREE-STATE OUTPUT
ICD2051-6
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ICD2051:1/95
Revision: April 11, 1995
ICD2051
Test Circuit
DEVICE UNDER TEST VDD 0.1 F CLOAD VDD CLK out
GND
Ordering Information
Ordering Code ICD2051
Note: 3. 0C to +70C
Package Name S1
Package Type 16-Pin SOIC
Operating Range Commercial[3]
Document #: 38-00402
Package Diagram
16-Lead Molded SOIC S1
(c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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